/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2020-2021.
 * Description: machine hisi platform header file
 * Author: yanbo <joey.yanbo@huawei.com>
 * Create: 2020-11-19
 */
#include <generated/autoconf.h>
#ifndef	HI_CHIP_REGS_H
#define	HI_CHIP_REGS_H

#include <linux/hal/hal_log.h>

#define REG_SCTL_RESET          0x50

#define REG_BASE_UART0		0xe4007000		/* p650 */
#define REG_UART0_IOSIZE	PAGE_ALIGN(0x1000)

#define REG_BASE_A9_PERI	0x1A000000		/* new */
#define REG_A9_PERI_IOSIZE	PAGE_ALIGN(0x10000)

/* CORTTX-A9 MPCORE MEMORY REGION */
#define REG_A9_PERI_SCU			0x0000
#define REG_A9_PERI_GIC_CPU		0x0100
#define REG_A9_PERI_GLOBAL_TIMER	0x0200
#define REG_A9_PERI_PRI_TIMER_WDT	0x0600
#define REG_A9_PERI_GIC_DIST		0x1000
#define REG_BASE_WDT		(REG_BASE_A9_PERI + REG_A9_PERI_PRI_TIMER_WDT)

/* SYSTEM CONTROL REG */
#define REG_SC_CTRL	0x000
#define REG_SC_SYSSTAT	0x004
#define REG_SC_ITMCTRL	0x008
#define REG_SC_IMSTAT	0x00C
#define REG_SC_XTALCTRL	0x010
#define REG_SC_PLLCTRL	0x014
#define REG_SC_PLLFCTRL	0x018
#define REG_SC_PERCTRL0	0x01C
#define REG_SC_PERCTRL1	0x020
#define REG_SC_PEREN	0x024
#define REG_SC_PERDIS	0x028
#define REG_SC_PERCLKEN	0x02C
#define REG_SC_RERSTAT	0x030
#define REG_SC_PERCTRL2	0x034
#define REG_SC_PERCTRL3	0x038
#define REG_SC_PERCTRL4	0x03C

/* HISI havent the regs as below */
#define REG_SC_PERLOCK	0x044
#define REG_SC_SYSID	0xEE0


#define REG_VALUE_SC_NOLOCK 0x1ACCE551
#define REG_VALUE_SC_LOCKED 0x00000001


/* SMI REG */
#define REG_SMI_BIDCYR1			0x000
#define REG_SMI_BWSTRDR1		0x004
#define REG_SMI_BWSTWRR1		0x008
#define REG_SMI_BWSTOENR1		0x00C
#define REG_SMI_BWSTWENR1		0x010
#define REG_SMI_BCR1			0x014
#define REG_SMI_BSR1			0x018
#define REG_SMI_BWSTBRDR1		0x01C
#define REG_SMI_BIDCYR0			0x0E0
#define REG_SMI_BWSTRDR0		0x0E4
#define REG_SMI_BWSTWRR0		0x0E8
#define REG_SMI_BWSTOENR0		0x0EC
#define REG_SMI_BWSTWENR0		0x0F0
#define REG_SMI_BCR0			0X0F4
#define REG_SMI_BSR0			0x0F8
#define REG_SMI_BWSTBRDR0		0x0FC
#define REG_SMI_SR			0x200
#define REG_SMI_CR			0x204

/* SMI */
#define SMI_SCSLR0_LOW_OFFSET  0x14
#define SMI_SCSLR1_LOW_OFFSET  0x18
#define SMI_SCSLR2_LOW_OFFSET  0x1c
#define SMI_SCSLR3_LOW_OFFSET  0x20
#define SMI_SCSLR4_LOW_OFFSET  0x24
#define SMI_SCSLR5_LOW_OFFSET  0x28
#define SMI_SCSLR6_LOW_OFFSET  0x2c
#define SMI_SCSLR7_LOW_OFFSET  0x30
#define SMI_SMSKR0_OFFSET      0x54
#define SMI_SMSKR1_OFFSET      0x58
#define SMI_SMSKR2_OFFSET      0x5c
#define SMI_SMSKR3_OFFSET      0x60
#define SMI_SMSKR4_OFFSET      0x64
#define SMI_SMSKR5_OFFSET      0x68
#define SMI_SMSKR6_OFFSET      0x6c
#define SMI_SMSKR7_OFFSET      0x70
#define SMI_SMTMGR_SET0_OFFSET 0x94
#define SMI_SMTMGR_SET1_OFFSET 0x98
#define SMI_SMTMGR_SET2_OFFSET 0x9C
#define SMI_FLASH_TRPD_OFFSET  0xA0
#define SMI_SMI_TRL_OFFSET     0xA4

#define REG_INTC_IRQSTATUS	0x000
#define REG_INTC_FIQSTATUS	0x004
#define REG_INTC_RAWSTATUS	0x008
#define REG_INTC_INTSELECT	0x00C
#define REG_INTC_INTENABLE	0x010
#define REG_INTC_INTENCLEAR	0x014
#define REG_INTC_SOFTINT	0x018
#define REG_INTC_SOFTINTCLEAR	0x01C
#define REG_INTC_PROTECTION	0x020

#define REG_TIMER_RELOAD	0x000
#define REG_TIMER_VALUE		0x004
#define REG_TIMER_CONTROL	0x008
#define REG_TIMER_INTCLR	0x00C
#define REG_TIMER_RIS		0x010
#define REG_TIMER_MIS		0x014
#define REG_TIMER_BGLOAD	0x018

#define REG_TIMER1_RELOAD        0x020
#define REG_TIMER1_VALUE         0x024
#define REG_TIMER1_CONTROL       0x028
#define REG_TIMER1_INTCLR        0x02C
#define REG_TIMER1_RIS           0x030
#define REG_TIMER1_MIS           0x034
#define REG_TIMER1_BGLOAD        0x038

/* TIMER23 */
#define REG_TIMER2_RELOAD_L	0x000
#define REG_TIMER2_RELOAD_H	0x004
#define REG_TIMER2_VALUE_L	0x008
#define REG_TIMER2_VALUE_H	0x00C
#define REG_TIMER2_CONTROL	0x010
#define REG_TIMER2_INTCLR	0x014
#define REG_TIMER2_RIS		0x018
#define REG_TIMER2_MIS		0x01C
#define REG_TIMER2_BGLOAD_L	0x020
#define REG_TIMER2_BGLOAD_H	0x024

#define REG_TIMER3_RELOAD_L     0x040
#define REG_TIMER3_RELOAD_H     0x044
#define REG_TIMER3_VALUE_L      0x048
#define REG_TIMER3_VALUE_H      0x04C
#define REG_TIMER3_CONTROL      0x050
#define REG_TIMER3_INTCLR       0x054
#define REG_TIMER3_RIS          0x058
#define REG_TIMER3_MIS          0x05C
#define REG_TIMER3_BGLOAD_L     0x060
#define REG_TIMER3_BGLOAD_H     0x064


/* TIMER45 */
#define REG_TIMER4_RELOAD_L	0x000
#define REG_TIMER4_RELOAD_H	0x004
#define REG_TIMER4_VALUE_L	0x008
#define REG_TIMER4_VALUE_H	0x00C
#define REG_TIMER4_CONTROL	0x010
#define REG_TIMER4_INTCLR	0x014
#define REG_TIMER4_RIS		0x018
#define REG_TIMER4_MIS		0x01C
#define REG_TIMER4_BGLOAD_L	0x020
#define REG_TIMER4_BGLOAD_H	0x024

#define REG_TIMER5_RELOAD_L     0x040
#define REG_TIMER5_RELOAD_H     0x044
#define REG_TIMER5_VALUE_L      0x048
#define REG_TIMER5_VALUE_H      0x04C
#define REG_TIMER5_CONTROL      0x050
#define REG_TIMER5_INTCLR       0x054
#define REG_TIMER5_RIS          0x058
#define REG_TIMER5_MIS          0x05C
#define REG_TIMER5_BGLOAD_L     0x060
#define REG_TIMER5_BGLOAD_H     0x064

/* TIMER67 */
#define REG_TIMER6_RELOAD_L	0x000
#define REG_TIMER6_RELOAD_H	0x004
#define REG_TIMER6_VALUE_L	0x008
#define REG_TIMER6_VALUE_H	0x00C
#define REG_TIMER6_CONTROL	0x010
#define REG_TIMER6_INTCLR	0x014
#define REG_TIMER6_RIS		0x018
#define REG_TIMER6_MIS		0x01C
#define REG_TIMER6_BGLOAD_L	0x020
#define REG_TIMER6_BGLOAD_H	0x024

#define REG_TIMER7_RELOAD_L     0x040
#define REG_TIMER7_RELOAD_H     0x044
#define REG_TIMER7_VALUE_L      0x048
#define REG_TIMER7_VALUE_H      0x04C
#define REG_TIMER7_CONTROL      0x050
#define REG_TIMER7_INTCLR       0x054
#define REG_TIMER7_RIS          0x058
#define REG_TIMER7_MIS          0x05C
#define REG_TIMER7_BGLOAD_L     0x060
#define REG_TIMER7_BGLOAD_H     0x064

/* TIMER89 */
#define REG_TIMER8_RELOAD_L	0x000
#define REG_TIMER8_RELOAD_H	0x004
#define REG_TIMER8_VALUE_L	0x008
#define REG_TIMER8_VALUE_H	0x00C
#define REG_TIMER8_CONTROL	0x010
#define REG_TIMER8_INTCLR	0x014
#define REG_TIMER8_RIS		0x018
#define REG_TIMER8_MIS		0x01C
#define REG_TIMER8_BGLOAD_L	0x020
#define REG_TIMER8_BGLOAD_H	0x024

#define REG_TIMER9_RELOAD_L     0x040
#define REG_TIMER9_RELOAD_H     0x044
#define REG_TIMER9_VALUE_L      0x048
#define REG_TIMER9_VALUE_H      0x04C
#define REG_TIMER9_CONTROL      0x050
#define REG_TIMER9_INTCLR       0x054
#define REG_TIMER9_RIS          0x058
#define REG_TIMER9_MIS          0x05C
#define REG_TIMER9_BGLOAD_L     0x060
#define REG_TIMER9_BGLOAD_H     0x064

#define MEM_BASE_DDR	0x80000000

#endif /* End of HI_CHIP_REGS_H */

